So if n 4 will not affect it, then D will not affect n 2 or n 3 either. If n 2 = 0 then n 3, the output of gate 3 will always be a 1 (since 0 NAND x = 1) regardless of what n 4, the third input to gate 3 may be. First we note that n 2 and n 3 are always inverses of each other. Once C lk is at a 1 and remains at a 1, changing D will not change n 2 or n 3. On the other hand, when C lk = 1 and if D = 1, then n 2 (which is equal to D ') will be 0, thus asserting S ' and setting the output latch Q to 1. So when C lk = 1 and if D = 0, then n 3 (which is equal to D) will be 0, thus asserting R ' and resetting the output latch Q to 0. When C lk changes to 1, n 2 will be equal to n 1 ' which is equal to D ', while n 3 will be equal to D. Similarly, n 1 = D since n 2 = 1 and the other input to gate 1 is n 4 which is D '. ![]() At the same time n 4 = D ' since one input to gate 4 is n 3 which is a 1 (1 NAND x = x'). Thus n 2 = n 3 = 1, which keeps the output latch, comprising of gates 5 and 6, in its current state.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |